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Developer’s Manual March, 2003 13-39
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.14.4.1 Loading IC During Cold Reset for Debug
The Figure 13-12 shows the actions necessary to download code into the instruction cache during a
cold reset for debug.
NOTE: In the Figure 13-12 hold_rst is a signal that gets set and cleared through JTAG When the
JTAG IR contains the SELDCSR instruction, the hold_rst signal is set to the value scanned into
DBG_SR[1].
Figure 13-12. Code Download During a Cold Reset For Debug
B1310-01
RESET# pin assert until hold_rst signal is set
TRST# resets JTAG IR to IDCODE
RESET invalidates IC
RESET#
TRST#
hold_rst
JTAG IR
Internal
RESET
RESET does not affect IC
hold_rst keeps internal
reset asserted
wait 2030 tcks after
RESET# asserted
Set hold_rst signal
Set Halt Mode bit
Processor branches
to address 0
clock 15 tcks after
last update_dr in LDIC mode
SELDCSRSELDCSR LDICIDCODE
Enter LDIC mode
Download code
Clear hold_rst signal
Keep Halt Mode bit set