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10-18 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.3.5 Two Word Coalesced Write
In Figure 10-8, two store byte instructions from the instruction stream have been coalesced into a
single write command in the write buffer. The bytes were stored to addresses 0x240 and 0x247.
The request is the same as the basic write word case except now the length is 0x3, indicating a two
word write. When the chipset or memory needs the data, DValid is asserted and two cycles later the
data is driven. In this case, however, only BE# bits 0 and 7 are asserted, indicating that the first and
last byte of the bus have valid data to be stored and the rest must not be written.
Figure 10-8. Two Word Coalesced Write
Wr Req
0x240
WrData
0x7E
ECC
0
1
1
0x0
0ns 25ns 50ns 75ns
MCLK
ADS#/LEN[2]
Lock/LEN[1]
W/R#/LEN[0]
A
DValid
CWF
D
BEn
DCB
Abort