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13-42 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
If it is necessary to download code into the instruction cache then:
2) Assert TRST#. This clears the Halt Mode bit allowing the instruction cache to be
invalidated.
3) Clear the Halt Mode bit through JTAG. This allows the instruction cache to be invalidated
by reset.
4) Place the LDIC JTAG instruction in the JTAG IR, then proceed with the normal code
download, using the Invalidate IC Line function before loading each line. This requires 10
packets to be downloaded per cache line instead of the 9 packets described in Section 13.14.3