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Developer’s Manual March, 2003 C-13
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Test Features
Figure C-3. JTAG Example
0001
1
00000
0
00
000
0000
000 0
000
0
TCK
TMS
Don’t Care
Don’t Care
NEW Inst = 0001
2
Old Inst
abcd
Don’t Care
Boundary Scan
Instruction Register
TDI
Parallel Out
IR Shift Reg
Register
TDO
Selected
DR Shift Reg
(
n
bits long)
4 bits long
dcba
0 1 2 3 4 5 -6 -5 -4 -3 -2
000000
nnnnn
PPPPPP PPPPP
-1
n
P
RESET
SELECT DR SCAN
SELECT IR SCAN
CAPTURE IR
SHIFT IR
SHIFT IR
EXIT1 IR
SHIFT IR
SHIFT IR
RESET
RUN TEST/ IDLE
c
b
a
d
b
a
1
c
1
0
0
a
a
1
0
b
0
0
0
1
UPDATE IR
SELECT DR SCAN
CAPTURE DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
SHIFT DR
UPDATE DR
RUN TEST/IDLE
RUN TEST/IDLE
RUN TEST/IDLE
RUN TEST/IDLE
SHIFT DR
EXIT1 DR
0
1
0
0
0
11
1
1