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C-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Test Features
C.2.4 TAP Test Data Registers
The Intel
®
80200 processor contains a device identification register and two test data registers
(Bypass and RUNBIST). Each test data register selected by the TAP controller is connected
serially between TDI and TDO. TDI is connected to the test data register’s most significant bit.
TDO is connected to the least significant bit. Data is shifted one bit position within the register
towards TDO on each rising edge of TCK. The following sections describe each of the test data
registers. See Figure C-5 for an example of loading the data register.
C.2.4.1. Device Identification Register
The Device Identification register is a 32-bit register containing the manufacturer’s identification
code, part number code and version code. The identification register is selected only by the idcode
instruction. When the TAP controller’s Test_Logic_Reset state is entered, idcode is automatically
loaded into the instruction register. The Device Identification register has a fixed parallel input
value that is loaded in the Capture_DR state.
The value of this register is shown in Table C-4.
C.2.4.2. Bypass Register
The required Bypass Register, a one-bit shift register, provides the shortest path between TDI and
TDO when either of a bypass, highz or clamp instructions are in effect. This allows rapid
movement of test data to and from other components on the board. This path can be selected when
no test operation is being performed. While the Bypass register is selected, data is transferred from
TDI to TDO without inversion.
Any instruction that does not make use of another test data register may select the Bypass register
as its active TDI to TDO path.
C.2.4.3. Boundary-Scan Register
The Boundary-Scan register is a required set of serial-shiftable register cells.
Table C-4. JTAG ID Register Value
Stepping Value
A0 0x09263013
A1 0x19263013
B0 0x29263013
C0 0x39263013
D0 0x49263013