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13-34 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.14 Downloading Code in the ICache
On the Intel
®
80200 processor, a 2K mini instruction cache, physically separate
1
from the 32K
main instruction cache can be used as an on-chip instruction RAM. An external host can download
code directly into either instruction cache through JTAG. In addition to downloading code, several
cache functions are supported.
The Intel
®
80200 processor supports loading the instruction cache during reset and during program
execution. Loading the instruction cache during normal program execution requires a strict
handshaking protocol between software running on the Intel
®
80200 processor and the external
host.
In the remainder of this section the term ‘instruction cache’ applies to either main or mini
instruction cache.
13.14.1 LDIC JTAG Command
The LDIC JTAG instruction selects the JTAG data register for loading code into the instruction
cache. The JTAG opcode for this instruction is ‘00111’. The LDIC instruction must be in the JTAG
instruction register in order to load code directly into the instruction cache through JTAG.
1. A cache line fill from external memory is never be written into the mini-instruction cache. The only way to load a line into the
mini-instruction cache is through JTAG.