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4-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Instruction Cache
4.2 Operation
4.2.1 Operation When Instruction Cache is Enabled
When the cache is enabled, it compares every instruction request address against the addresses of
instructions that it is currently holding. If the cache contains the requested instruction, the access
“hits” the cache, and the cache returns the requested instruction. If the cache does not contain the
requested instruction, the access “misses” the cache, and the cache requests a fetch from external
memory of the 8-word line (32 bytes) that contains the requested instruction using the fetch policy
described in Section 4.2.3. As the fetch returns instructions to the cache, they are placed in one of
two fetch buffers and the requested instruction is delivered to the instruction decoder.
A fetched line is written into the cache if it is cacheable. Code is designated as cacheable when the
Memory Management Unit (MMU) is disabled or when the MMU is enable and the cacheable (C)
bit is set to 1 in its corresponding page. See Chapter 3, “Memory Management” for a discussion on
page attributes.
Note that an instruction fetch may “miss” the cache but “hit” one of the fetch buffers. When this
happens, the requested instruction is delivered to the instruction decoder in the same manner as a
cache “hit.”
4.2.2 Operation When The Instruction Cache Is Disabled
Disabling the cache prevents any lines from being written into the instruction cache. Although the
cache is disabled, it is still accessed and may generate a “hit” if the data is already in the cache.
Disabling the instruction cache does not disable instruction buffering that may occur within the
instruction fetch buffers. Two 8-word instruction fetch buffers are always enabled in the cache
disabled mode. So long as instruction fetches continue to “hit” within either buffer (even in the
presence of forward and backward branches), no external fetches for instructions are generated. A
miss causes one or the other buffer to be filled from external memory using the fill policy described
in Section 4.2.3.