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6-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
6.1.3 Write Buffer and Fill Buffer Overview
The Intel
®
80200 processor employs an eight entry write buffer, each entry containing 16 bytes.
Stores to external memory are first placed in the write buffer and subsequently taken out when the
bus is available.
The write buffer supports the coalescing of multiple store requests to external memory. An
incoming store may coalesce with any of the eight entries.
The fill buffer holds the external memory request information for a data cache or mini-data cache
fill or non-cacheable read request. Up to four 32-byte read request operations can be outstanding in
the fill buffer before the Intel
®
80200 processor needs to stall.
The fill buffer has been augmented with a four entry pend buffer that captures data memory
requests to outstanding fill operations. Each entry in the pend buffer contains enough data storage
to hold one 32-bit word, specifically for store operations. Cacheable load or store operations that
hit an entry in the fill buffer get placed in the pend buffer and are completed when the associated
fill completes. Any entry in the pend buffer can be pended against any of the entries in the fill
buffer; multiple entries in the pend buffer can be pended against a single entry in the fill buffer.
Pended operations complete in program order.