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Developer’s Manual March, 2003 10-1
External Bus
10
10.1 General Description
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the
ARM* Architecture V5TE) bus is a split bus, with separate request and data buses. It is designed
primarily as the memory and I/O bus for the Intel
®
80200 processor, not as a general purpose
multi-master bus, although it is possible to have several masters on it efficiently. It is deeply
pipelined and works well with deeply pipelined memory technologies, with the memory sharing
the data bus with the Intel
®
80200 processor, or with the memory on a separate chipset bus.
Figure 10-1 shows a typical system; this configuration allows the chipset to avoid having a second
64-bit memory bus in addition to the 64-bit Intel
®
80200 processor data bus, with significant
savings in chipset cost.
Figure 10-1. Typical System
Intel
®
80200
SDRAM
ROM/
Flash
Chipset
Request
Data
SDRAM Ctrl
Adr/Ctl
Data
PCI
Hold
Processor
based on
Intel® XScale™
Microarchitecture