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Developer’s Manual March, 2003 13-11
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
When DBR1 is programmed as a data address mask, it is used in conjunction with the address in
DBR0. The bits set in DBR1 are ignored by the processor when comparing the address of a
memory access with the address in DBR0. Using DBR1 as a data address mask allows a range of
addresses to generate a data breakpoint. When DBR1 is selected as a data address mask, it is
unaffected by the E1 field of DBCON. The mask is used only when DBR0 is enabled.
When DBR1 is programmed as a second data address breakpoint, it functions independently of
DBR0. In this case, the DBCON.E1 controls DBR1.
A data breakpoint is triggered if the memory access matches the access type and the address of any
byte within the memory access matches the address in DBRx. For example, LDR triggers a
breakpoint if DBCON.E0 is 0b10 or 0b11, and the address of any of the 4 bytes accessed by the
load matches the address in DBR0.
The processor does not trigger data breakpoints for the PLD instruction or any CP15, register
7,8,9,or 10 functions. Any other type of memory access can trigger a data breakpoint. For data
breakpoint purposes the SWP and SWPB instructions are treated as stores - they do not cause a
data breakpoint if the breakpoint is set up to break on loads only and an address match occurs.
On unaligned memory accesses, breakpoint address comparison is done on a word-aligned address
(aligned down to word boundary).
When a memory access triggers a data breakpoint, the breakpoint is reported after the access is
issued. The memory access is not aborted by the processor. The actual timing of when the access
completes with respect to the start of the debug handler depends on the memory configuration.
On a data breakpoint, the processor generates a debug exception and re-directs execution to the
debug handler before the next instruction executes. The processor reports the data breakpoint by
setting the DCSR.MOE to 0b010. The link register of a data breakpoint is always PC (of the next
instruction to execute) + 4, regardless of whether the processor is configured for monitor mode or
halt mode.
13.7 Software Breakpoints
Mnemonics: BKPT (See ARM Architecture Reference Manual, ARMv5T)
Operation: If DCSR[31] = 0, BKPT is a nop;
If DCSR[31] =1, BKPT causes a debug exception
The processor handles the software breakpoint as described in Section 13.5, “Debug Exceptions”
on page 13-6.