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3-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Memory Management
3.4 Control
3.4.1 Invalidate (Flush) Operation
The entire instruction and data TLB can be invalidated at the same time with one command or they
can be invalidated separately. An individual entry in the data or instruction TLB can also be
invalidated. See Table 7-13, “TLB Functions” on page 7-13 for a listing of commands supported
by the Intel
®
80200 processor.
Globally invalidating a TLB does not affect locked TLB entries. However, the invalidate-entry
operations can invalidate individual locked entries. In this case, the locked entry remains in the
TLB, but never “hits” on an address translation. Effectively, a hole is in the TLB. This situation
may be rectified by unlocking the TLB.
3.4.2 Enabling/Disabling
The MMU is enabled by setting bit 0 in coprocessor 15, register 1 (Control Register).
When the MMU is disabled, accesses to the instruction cache default to cacheable and all accesses
to data memory are made non-cacheable.
A recommended code sequence for enabling the MMU is shown in Example 3-1 on page 3-6.
Example 3-1. Enabling the MMU
; This routine provides software with a predictable way of enabling the MMU.
; After the CPWAIT, the MMU is guaranteed to be enabled. Be aware
; that the MMU will be enabled sometime after MCR and before the instruction
; that executes after the CPWAIT.
; Programming Note: This code sequence requires a one-to-one virtual to
; physical address mapping on this code since
; the MMU may be enabled part way through. This would allow the instructions
; after MCR to execute properly regardless the state of the MMU.
MRC P15,0,R0,C1,C0,0; Read CP15, register 1
ORR R0, R0, #0x1; Turn on the MMU
MCR P15,0,R0,C1,C0,0; Write to CP15, register 1
; For a description of CPWAIT, see
; Section 2.3.3, “Additions to CP15 Functionality” on page 2-11
CPWAIT
; The MMU is guaranteed to be enabled at this point; the next instruction or
; data address will be translated.