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Developer’s Manual March, 2003 13-1
Software Debug
13
This chapter describes software debug and related features in the Intel
®
80200 processor based on
Intel
®
XScale
™
microarchitecture (compliant with ARM* Architecture V5TE), namely:
• debug modes, registers and exceptions
• a serial debug communication link via the JTAG interface
• a trace buffer
• a mechanism to load the instruction cache through JTAG
• Debug Handler SW requirements and suggestions
13.1 Definitions
debug handler -is an event handler that runs on the Intel
®
80200 processor, when a debug event
occurs.
debugger - is software that runs on a host system outside of the Intel
®
80200 processor.
13.2 Debug Registers
CP15 Registers
CRn = 14; CRm = 8: instruction breakpoint register 0 (IBCR0)
CRn = 14; CRm = 9: instruction breakpoint register 1 (IBCR1)
CRn = 14; CRm = 0: data breakpoint register 0 (DBR0)
CRn = 14; CRm = 3: data breakpoint register 1 (DBR1)
CRn = 14; CRm = 4: data breakpoint control register (DBCON)
CP15 registers are accessible using MRC and MCR. CRn and CRm specify the register to access.
The opcode_1 and opcode_2 fields are not used and should be set to 0.
CP14 Registers
CRn = 8; CRm = 0: TX Register (TX)
CRn = 9; CRm = 0: RX Register (RX)
CRn = 10; CRm = 0: Debug Control and Status Register (DCSR)
CRn = 11; CRm = 0: Trace Buffer Register (TBREG)
CRn = 12; CRm = 0: Checkpoint Register 0 (CHKPT0)
CRn = 13; CRm = 0: Checkpoint Register 1 (CHKPT1)
CRn = 14; CRm = 0: TXRX Control Register (TXRXCTRL)
CP14 registers are accessible using MRC, MCR, LDC and STC (CDP to any CP14 registers cause
an undefined instruction trap). The CRn field specifies the number of the register to access. The
CRm, opcode_1, and opcode_2 fields are not used and should be set to 0.
Software access to all debug registers must be done in privileged mode. User mode access generates
an undefined instruction exception. Specifying registers which do not exist has unpredictable results.
The TX and RX registers, certain bits in the TXRXCTRL register, and certain bits in the DCSR can
be accessed by a debugger through the JTAG interface.