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7-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
7.2 CP15 Registers
Table 7-3 lists the CP15 registers implemented in the Intel
®
80200 processor.
Table 7-3. CP15 Registers
Register (CRn) Opcode_2 Access Description
0 0 Read / Write-Ignored ID
0 1 Read / Write-Ignored Cache Type
1 0 Read / Write Control
1 1 Read / Write Auxiliary Control
2 0 Read / Write Translation Table Base
3 0 Read / Write Domain Access Control
4 - Unpredictable Reserved
5 0 Read / Write Fault Status
6 0 Read / Write Fault Address
7 0 Read-unpredictable / Write Cache Operations
8 0 Read-unpredictable / Write TLB Operations
9 0 Read-unpredictable / Write Cache Lock Down
10 0 Read / Write TLB Lock Down
11 - 12 - Unpredictable Reserved
13 0 Read / Write Process ID (PID)
14 0 Read / Write Breakpoint Registers
15 0 Read / Write (CRm = 1) CP Access