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Developer’s Manual March, 2003 iii
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Contents
1 Introduction .............................................................................................. 1
1.1 Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture High-Level Overview.........1
1.1.1 ARM* Architecture Compliance ...................................................................................1
1.1.2 Features.......................................................................................................................2
1.1.2.1 Multiply/Accumulate (MAC) ......................................................................2
1.1.2.2 Memory Management...............................................................................3
1.1.2.3 Instruction Cache......................................................................................3
1.1.2.4 Branch Target Buffer ................................................................................3
1.1.2.5 Data Cache...............................................................................................3
1.1.2.6 Power Management..................................................................................4
1.1.2.7 Interrupt Controller....................................................................................4
1.1.2.8 Bus Controller ...........................................................................................4
1.1.2.9 Performance Monitoring ...........................................................................4
1.1.2.10 Debug .......................................................................................................4
1.1.2.11 JTAG.........................................................................................................4
1.2 Terminology and Conventions......................................................................................................5
1.2.1 Number Representation...............................................................................................5
1.2.2 Terminology and Acronyms .........................................................................................5
1.3 Other Relevant Documents ..........................................................................................................6
2 Programming Model ................................................................................ 1
2.1 ARM* Architecture Compliance ....................................................................................................1
2.2 ARM* Architecture Implementation Options .................................................................................1
2.2.1 Big Endian versus Little Endian ...................................................................................1
2.2.2 26-Bit Code..................................................................................................................1
2.2.3 Thumb* ........................................................................................................................1
2.2.4 ARM* DSP-Enhanced Instruction Set..........................................................................2
2.2.5 Base Register Update..................................................................................................2
2.3 Extensions to ARM* Architecture..................................................................................................3
2.3.1 DSP Coprocessor 0 (CP0)...........................................................................................3
2.3.1.1 Multiply With Internal Accumulate Format ................................................4
2.3.1.2 Internal Accumulator Access Format........................................................7
2.3.2 New Page Attributes ....................................................................................................9
2.3.3 Additions to CP15 Functionality.................................................................................11
2.3.4 Event Architecture .....................................................................................................12
2.3.4.1 Exception Summary................................................................................12
2.3.4.2 Event Priority ..........................................................................................12
2.3.4.3 Prefetch Aborts .......................................................................................13
2.3.4.4 Data Aborts.............................................................................................14
2.3.4.5 Events from Preload Instructions............................................................16
2.3.4.6 Debug Events .........................................................................................16
3 Memory Management .............................................................................. 1
3.1 Overview.......................................................................................................................................1
3.2 Architecture Model........................................................................................................................2
3.2.1 Version 4 vs. Version 5................................................................................................2
3.2.2 Memory Attributes........................................................................................................2