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Developer’s Manual March, 2003 13-23
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.11.6.1 RX Write Logic
The RX write logic (Figure 13-6) serves 4 functions:
1) Enable the debugger write to RX - the logic ensures only new, valid data from the debugger
is written to RX. In particular, when the debugger polls TXRXCTRL[31] to see whether the
debug handler has read the previous data from RX. The JTAG state machine must go through
Update_DR, which should not modify RX.
2) Clear DBG_REG[34] - mainly to support high-speed download. During high-speed
download, the debugger continuously scan in a data to send to the debug handler and sets
DBG_REG[34] to signal the data is valid. Since DBG_REG[34] is never cleared by the
debugger in this case, the ‘0’ to ‘1’ transition used to enable the debugger write to RX would
not occur.
3) Set TXRXCTRL[31] - When the debugger writes new data to RX, the logic automatically
sets TXRXCTRL[31], signalling to the debug handler that the data is valid.
4) Set the overflow flag (TXRXCTRL[30] - During high-speed download, the debugger does
not poll to see if the handler has read the previous data. If the debug handler stalls long
enough, the debugger may overwrite the previous data before the handler can read it. The logic
sets the overflow flag when the previous data has not been read yet, and the debugger has just
written new data to RX.
Figure 13-5. RX Write Logic
Intel® 80200 Processor
DBG_REG[34]
TXRXCTRL[31]
Clear DBG_REG[34]
RX write enable
set TXRXCTRL[31]
set overflow flag
(TXRXCTRL[30])
CLK