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11-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Bus Controller
Error reporting may be enabled with the BCUCTL register, described in Section 11.4.1. If enabled,
single bit errors cause the BCU to assert an interrupt to the Interrupt Controller Unit (ICU). If the
interrupt is not enabled in the ICU, it is not propagated to the core. This interrupt may be cleared by
software by writing to the BCU Control Register (see Section 11.4.1) If a masked interrupt is not
cleared by software, it interrupts the core if software ever unmasks it.
Although single-bit errors can be corrected by the BCU, the software may choose to take the
additional step of scrubbing the offending memory location. To accomplish this, the software
needs to write the correct data back to the location. The BCU logs sufficient information in its
registers (ELOGx and ECARx) to enable software to re-issue the load that uncovered the problem.
Single-bit errors detected during a RMW are corrected and written back if single-bit-correction is
enabled. The BCU still reports the error if enabled, but software does not need to scrub the
location.
Single bit errors may also be detected in the received ECC itself. In this case, the BCU doesn’t
need to modify the received data, but it still reports the error if enabled. Software can scrub the
memory’s ECC by simply writing to it. The BCU automatically generates and writes the correct
ECC value.
If a multi-bit error is detected, the BCU requests an exception of the core. The exact exception
triggered depends on the data’s destination. For example, a code fetch that received a multi-bit
error would result in a Prefetch Abort if the processor attempted to execute the code.
If the BCU receives a bus abort (see Section 10.2.6, “Abort” on page 10-11 and Section 11.3.1,
“Bus Aborts” on page 11-2) and an ECC error on the same cycle, it ignores the ECC information
for the cycle and process the bus abort normally.
Any ECC error that elicits a Prefetch or Data abort from the BCU is the final error associated with
a data burst. The BCU accepts the remaining data from the bus, but ignores it and does not perform
ECC checks.