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Developer’s Manual March, 2003 6-1
Data Cache
6
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the
ARM* Architecture V5TE) data cache enhances performance by reducing the number of data
accesses to and from external memory. There are two data cache structures in the Intel
®
80200
processor, a 32 Kbyte data cache and a 2 Kbyte mini-data cache. An eight entry write buffer and a
four entry fill buffer are also implemented to decouple the Intel
®
80200 processor instruction
execution from external memory accesses, which increases overall system performance.
6.1 Overviews
6.1.1 Data Cache Overview
The data cache is a 32-Kbyte, 32-way set associative cache; this means there are 32 sets with each
set containing 32 ways. Each way of a set contains 32 bytes (one cache line) and one valid bit.
There also exist two dirty bits for every line, one for the lower 16 bytes and the other one for the
upper 16 bytes. When a store hits the cache the dirty bit associated with it is set. The replacement
policy is a round-robin algorithm and the cache also supports the ability to reconfigure each line as
data RAM.
Figure 6-1, “Data Cache Organization” on page 6-2 shows the cache organization and how the data
address is used to access the cache.
Cache policies may be adjusted for particular regions of memory by altering page attribute bits in
the MMU descriptor that controls that memory. See Section 3.2.2 for a description of these bits.
The data cache is virtually addressed and virtually tagged. It supports write-back and write-through
caching policies. The data cache always allocates a line in the cache when a cacheable read miss
occurs and allocates a line into the cache on a cacheable write miss when write allocate is specified
by its page attribute. Page attribute bits determine whether a line gets allocated into the data cache
or mini-data cache.