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Developer’s Manual March, 2003 4-5
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Instruction Cache
4.2.6 Instruction Fetch Latency
Because the Intel
®
80200 processor core is clocked at a multiple of the external bus clock, and the
two clocks are truly asynchronous, an exact fetch latency is difficult to derive. In general, if a fetch
can be directly issued (no other memory accesses are intervening), then the delay to the first
instruction is approximately (8 + W) bus clocks, where W is number of memory wait states.
As an example: in a system with 2-wait-state memory (W = 2), an unoccluded fetch would require
about 10 bus clocks to get the first instruction. If this system were running with a core/bus clock
ratio of 6, then the core would perceive this as a latency of about 60 cycles.
These numbers are best case and assume that no other active memory transactions exist. Refer to
Chapter 10, “External Bus” for more information on External Bus signal definitions and request
timings.
4.2.7 Instruction Cache Coherency
The instruction cache does not detect modification to program memory by loads, stores or actions
of other bus masters. Several situations may require program memory modification, such as
uploading code from disk.
The application program is responsible for synchronizing code modification and invalidating the
cache. In general, software must ensure that modified code space is not accessed until modification
and invalidating are completed.
To achieve cache coherence, instruction cache contents can be invalidated after code modification
in external memory is complete. Refer to Section 4.3.3, “Invalidating the Instruction Cache” on
page 4-7 for the proper procedure in invalidating the instruction cache.
If the instruction cache is not enabled, or code is being written to a non-cacheable region, software
must still invalidate the instruction cache before using the newly-written code. This precaution
ensures that state associated with the new code is not buffered elsewhere in the processor, such as
the fetch buffers or the BTB.
Naturally, when writing code as data, care must be taken to force it completely out of the processor
into external memory before attempting to execute it. If writing into a non-cacheable region,
flushing the write buffers is sufficient precaution (see Section 7.2.8 for a description of this
operation). If writing to a cacheable region, then the data cache should be submitted to a
Clean/Invalidate operation (see Section 6.3.3.1) to ensure coherency.