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10-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.2.2 Data Bus
Some time after a request is made on the request bus, data must be transferred for that request on
the data bus. Each request has a corresponding transaction (one or more cycles) on the data bus.
Data bus transactions must occur in the same order as the requests were made. The delay between a
request going out and the data coming back to or being driven from the bus master is arbitrary. No
explicit wait-state insertion is needed.
All data on the 64-bit data bus is read or written in its natural location within an aligned 64-bit
memory block. In little endian mode, 64-bit bus (big endian and 32-bit busses are covered later)
bits 7-0 of D always correspond to a byte with low address bits (2:0) of “000”, and bits 63-56
always correspond to a byte with low address bits of “111”. As an example, a word (32-bit) read to
address 0x24004 would need to be returned to the core with the most significant byte on bits
[63:56] and the least significant byte on bits [39:32]. For a byte write to location 0x3703, the valid
data byte would be driven out on bits [31:24] of D (and only bit 3 of the BE# would be asserted).
Each data transaction consists of one or more data cycles. Each data cycle begins with the assertion
of DValid to indicate to the Intel
®
80200 processor that the next cycle of data is going to be
transferred, followed two clock cycles later by the data transfer (read or write data) on the D, BE#
(for writes only), and DCB buses.
All lines in D must be driven during a data transaction: on writes the Intel
®
80200 processor will
drive them, on reads they must be driven by the addressed slave. If the read request was for less
than a full bus-width of data (example: a byte read), the other lines should be driven with some
binary value.
If a read is directed to a slave that implements ECC, a full bus-width of valid data (64 bits) must be
returned, without regard for the requested size. For example, even if just a byte is requested from
ECC memory, the memory should still return eight bytes of data. This restriction guarantees that
the Intel
®
80200 processor will be able to compute ECC on the data; see Section 10.2.7 for more
information about ECC.
DValid for a transaction may be asserted no earlier than the clock after the transaction request. In
other words, if the Intel
®
80200 processor asserts ADS# at cycle N, it must not receive a matching
DValid until at least cycle N+2. See Figure 10-11 for an example of this minimum-wait timing.
For a single-word read returning to the core, the transaction would consist of the DValid signal
being asserted high and sampled on clock edge n, and the data being sampled by the Intel
®
80200
processor from the D bus on clock edge n+2 (see Figure 10-4).
For a read burst request multiple data cycles are needed. On a 64-bit bus an eight word burst read
would be four data cycles. The data cycles are independent and can occur back-to-back, or spread
out with any delay between the cycles. Each cycle consists of DValid being asserted followed two
cycles later by the corresponding data. This can be overlapped, such that DValid for one data cycle
is being asserted while the D for another data cycle is being driven on the bus. A typical burst
would be DValid asserted for four contiguous cycles (n, n+1, n+2, n+3) with the data for that burst
being driven in four contiguous cycles delayed two cycles from the DValid (n+2, n+3, n+4, n+5),
as shown in Figure 10-5.
If the part has been configured to use a 32-bit data bus, then D[63:32] and DCB[7:0] are floated on
all writes. Also, bits in BE#[7:4] drives a binary (‘1’ or ‘0’) value. It is suggested that DCB and the
upper bits of D be pulled-down on 32-bit data bus systems.