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12-12 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Performance Monitoring
12.7 Examples
In this example, the events selected with the Instruction Cache Efficiency mode are monitored and
CCNT is used to measure total execution time. Sampling time ends when PMN0 overflows which
generates an IRQ interrupt.
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI was 2.4.
Example 12-1. Configuring the Performance Monitor
; Configure PMNC with the following values:
; evtCount0 = 7, evtCount1 = 0instruction cache efficiency
; inten = 0x7set all counters to trigger an interrupt on
overflow
; C = 1 reset CCNT register
; P = 1 reset PMN0 and PMN1 registers
; E = 1 enable counting
MOV R0,#0x7777
MCR P14,0,R0,C0,c0,0 ; write R0 to PMNC
; Counting begins
Example 12-2. Interrupt Handling
IRQ_INTERRUPT_SERVICE_ROUTINE:
; Assume that performance counting interrupts are the only IRQ in the system
MRC P14,0,R1,C0,c0,0 ; read the PMNC register
BIC R2,R1,#1 ; clear the enable bit
MCR P14,0,R2,C0,c0,0 ; clear interrupt flag and disable counting
MRC P14,0,R3,C1,c0,0 ; read CCNT register
MRC P14,0,R4,C2,c0,0 ; read PMN0 register
MRC P14,0,R5,C3,c0,0 ; read PMN1 register
<process the results>
SUBSPC,R14,#4 ; return from interrupt
Example 12-3. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction