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Developer’s Manual March, 2003 10-11
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.2.6 Abort
If for any reason a request made by the Intel
®
80200 processor can not be completed, it must be
aborted. At the same time as the assertion DValid for any data cycle of any transaction, Abort can
be asserted. This has the effect of ending that transaction at that data cycle. The Intel
®
80200
processor saves the address of the aborted transaction and take an exception.
If Abort is asserted at the same time as DValid of the first data cycle of a given bus transaction, no
data is sampled or driven by the Intel
®
80200 processor off of the D bus two cycles after the Abort
is asserted. That transaction is finished as soon as the Abort signal is sampled and no further data is
transferred.
On a transaction with multiple data cycles, Abort can be asserted along with DValid at any time
during the transaction. Data is read from or driven to the data bus two cycles after each of the
pre-abort DValids.
For a write transaction, no data is driven at the clock edge two cycles after Abort is sampled. For a
read transaction, external logic must drive the data buses (D and DCB) to a valid level two cycles
after Abort is sampled. At that point the transaction is cancelled and no further data or DValids are
expected for that transaction.
For burst transactions, care must be taken to end the transaction when the Abort is asserted. If a
cache line fill (four data cycles on a 64-bit bus) has Abort asserted along with the first DValid, the
Intel
®
80200 processor ends the transaction and expect that none of the other data cycles for the
burst occurs. If the chipset or memory were to assert DValid at that point and continue to send data,
the Intel
®
80200 processor would assume that data was associated with the next read request after
the cache line fill that was aborted. If there had been no read request after the cache line fill, those
extra data cycles would cause unpredictable results.
Abort must not be asserted for two consecutive cycles. In other words, back-to-back aborts are not
permitted, and causes incorrect operation if they occur. The Data Bus portion of the bus must have
a dead cycle after any abort cycle. That is: DValid must not be asserted the cycle after Abort has
been asserted.