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B-44 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Optimization Guide
B.5.7 Scheduling MRS and MSR Instructions
The MRS instruction has an issue latency of 1 cycle and a result latency of 2 cycles. The MSR
instruction has an issue latency of 2 cycles (6 if updating the mode bits) and a result latency of 1
cycle.
Consider the code sample:
mrs r0, cpsr
orr r0, r0, #1
add r1, r2, r3
The ORR instruction above would incur a 1 cycle stall due to the 2-cycle result latency of the
MRS instruction. In the code example above, the ADD instruction can be moved before the ORR
instruction to prevent this stall.
B.5.8 Scheduling CP15 Coprocessor Instructions
The MRC instruction has an issue latency of 1 cycle and a result latency of 3 cycles. The MCR
instruction has an issue latency of 1 cycle.
Consider the code sample:
add r1, r2, r3
mrc p15, 0, r7, C1, C0, 0
mov r0, r7
add r1, r1, #1
The MOV instruction above would incur a 2-cycle latency due to the 3-cycle result latency of the
mrc instruction. The code shown above can be rearranged as follows to avoid these stalls:
mrc p15, 0, r7, C1, C0, 0
add r1, r2, r3
add r1, r1, #1
mov r0, r7