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Developer’s Manual March, 2003 12-1
Performance Monitoring
12
This chapter describes the performance monitoring facility of the Intel
®
80200 processor based on
Intel
®
XScale
™
microarchitecture (compliant with the ARM* Architecture V5TE). The events that
are monitored can provide performance information for compiler writers, system application
developers and software programmers.
12.1 Overview
The Intel
®
80200 processor hardware provides two 32-bit performance counters that allow two
unique events to be monitored simultaneously. In addition, the Intel
®
80200 processor implements
a 32-bit clock counter that can be used in conjunction with the performance counters; its sole
purpose is to count the number of core clock cycles which is useful in measuring total execution
time.
The Intel
®
80200 processor can monitor either occurrence events or duration events. When
counting occurrence events, a counter is incremented each time a specified event takes place and
when measuring duration, a counter counts the number of processor clocks that occur while a
specified condition is true. If any of the three counters overflow, an IRQ or FIQ is generated if it is
enabled. (IRQ or FIQ selection is programmed in the interrupt controller.) Each counter has its own
interrupt enable. The counters continue to monitor events even after an overflow occurs, until
disabled by software.
Each of these counters can be programmed to monitor any one of various events.
To further augment performance monitoring, the Intel
®
80200 processor clock counter can be used
to measure the executing time of an application. This information combined with a duration event
can feedback a percentage of time the event occurred with respect to overall execution time.
Each of the three counters and the performance monitoring control register are accessible through
Coprocessor 14 (CP14), registers 0-3. Refer to Section 7.3.1, “Registers 0-3: Performance
Monitoring” on page 7-20 for more details on accessing these registers with MRC, MCR, LDC,
and STC coprocessor instructions. Access is allowed in privileged mode only.