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2-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Programming Model
2.2.4 ARM* DSP-Enhanced Instruction Set
The Intel
®
80200 processor implements ARM DSP-enhanced instruction set, which is a set of
instructions that boost the performance of signal processing applications. There are new multiply
instructions that operate on 16-bit data values and new saturation instructions. Some of the new
instructions are:
• SMLAxy 32<=16x16+32
• SMLAWy 32<=32x16+32
• SMLALxy 64<=16x16+64
• SMULxy 32<=16x16
• SMULWy 32<=32x16
• QADD adds two registers and saturates the result if an overflow occurred
• QDADD doubles and saturates one of the input registers then add and saturate
• QSUB subtracts two registers and saturates the result if an overflow occurred
• QDSUB doubles and saturates one of the input registers then subtract and saturate
The Intel
®
80200 processor also implements LDRD, STRD and PLD instructions with the
following implementation notes:
• PLD is interpreted as a read operation by the MMU and is ignored by the data breakpoint unit,
i.e., PLD never generates data breakpoint events.
• PLD to a non-cacheable page performs no action. Also, if the targeted cache line is already
resident, this instruction has no affect.
• Both LDRD and STRD instructions generation an alignment exception when the address bits
[2:0] = 0b100.
MCRR and MRRC are only supported on the Intel
®
80200 processor when directed to coprocessor
0 and are used to access the internal accumulator. See Section 2.3.1.2 for more information. Access
to any other coprocessor besides 0x0 are undefined.
2.2.5 Base Register Update
If a data abort is signalled on a memory instruction that specifies writeback, the contents of the
base register is not updated. This holds for all load and store instructions. This behavior matches
that of the first generation Intel
®
StrongARM* processor and is referred to in the ARM V5
architecture as the Base Restored Abort Model.