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6-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
6.2.3.2 Read Miss Policy
The following sequence of events occurs when a cacheable (see Section 6.2.3.1, “Cacheability” on
page 6-5) load operation misses the cache:
1. The fill buffer is checked to see if an outstanding fill request already exists for that line.
If so, the current request is placed in the pending buffer and waits until the previously
requested fill completes, after which it accesses the cache again, to obtain the request data and
returns it to the destination register.
If there is no outstanding fill request for that line, the current load request is placed in the fill
buffer and a 32-byte external memory read request is made. If the pending buffer or fill buffer
is full, the Intel
®
80200 processor stalls until an entry is available.
2. A line is allocated in the cache to receive the 32-bytes of fill data. The line selected is
determined by the round-robin pointer (see Section 6.2.4, “Round-Robin Replacement
Algorithm” on page 6-8). The line chosen may contain a valid line previously allocated in the
cache. In this case both dirty bits are examined and if set, the four words associated with a
dirty bit that’s asserted are written back to external memory as a four word burst operation.
3. When the data requested by the load is returned from external memory, it is immediately sent
to the destination register specified by the load. A system that returns the requested data back
first, with respect to the other bytes of the line, obtains the best performance.
4. As data returns from external memory it is written into the cache in the previously allocated
line.
A load operation that misses the cache and is NOT cacheable makes a request from external
memory for the exact data size of the original load request. For example, LDRH requests exactly
two bytes from external memory, LDR requests 4 bytes from external memory, etc. This request is
placed in the fill buffer until, the data is returned from external memory, which is then forwarded
back to the destination register(s).