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Developer’s Manual March, 2003 2-15
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Programming Model
Imprecise data aborts
• A data cache parity error is imprecise; the extended Status field of the Fault Status Register is
set to 0xb11000.
• All external data aborts except for those generated on a data MMU translation are imprecise.
The Fault Address Register for all imprecise data aborts is undefined and R14_ABORT is the
address of the next instruction to execute + 4, which is the same for both ARM and Thumb mode.
The Intel
®
80200 processor generates external data aborts on multi-bit ECC errors and when the
Abort pin is asserted on memory transactions. (See Chapter 11, “Bus Controller” for more details.)
An external data abort can occur on non-cacheable loads, reads into the cache, cache evictions, or
stores to external memory.
Although the Intel
®
80200 processor guarantees the Base Restored Abort Model for precise aborts,
it cannot do so in the case of imprecise aborts. A Data Abort handler may encounter an updated
base register if it is invoked because of an imprecise abort.
Imprecise data aborts may create scenarios that are difficult for an abort handler to recover. Both
external data aborts and data cache parity errors may result in corrupted data in the targeted
registers. Because these faults are imprecise, it is possible that the corrupted data has been used
before the Data Abort fault handler is invoked. Because of this, software should treat imprecise
data aborts as unrecoverable.
Note that even memory accesses marked as “stall until complete” (see Section 3.2.2.4) can result in
imprecise data aborts. For these types of accesses, the fault is somewhat less imprecise than the
general case: it is guaranteed to be raised within three instructions of the instruction that caused it.
In other words, if a “stall until complete” LD or ST instruction triggers an imprecise fault, then that
fault is seen by the program within three instructions.
With this knowledge, it is possible to write code that accesses “stall until complete” memory with
impunity. Simply place several NOP instructions after such an access. If an imprecise fault occurs,
it happens during the NOPs; the data abort handler sees identical register and memory state as it
would with a precise exception, and so should be able to recover. An example of this is shown in
Example 2-2 on page 2-15.
Of course, if a system design precludes events that could cause external aborts, then such
precautions are not necessary.
Example 2-2. Shielding Code from Potential Imprecise Aborts
;; Example of code that maintains architectural state through the
;; window where an imprecise fault might occur.
LD R0, [R1] ; R1 points to stall-until-complete
; region of memory
NOP
NOP
NOP
; Code beyond this point is guaranteed not to see any aborts
; from the LD.