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Developer’s Manual March, 2003 B-23
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Optimization Guide
B.4.2.7. Literal Pools
The Intel
®
80200 processor does not have a single instruction that can move all literals (a constant
or address) to a register. One technique to load registers with literals in the Intel
®
80200 processor
is by loading the literal from a memory location that has been initialized with the constant or
address. These blocks of constants are referred to as literal pools. See Section B.3, “Basic
Optimizations” for more information on how to do this. It is advantageous to place all the literals
together in a pool of memory known a literal pool. These data blocks are located in the text or code
address space so that they can be loaded using PC relative addressing. However, references to the
literal pool area load the data into the data cache instead of the instruction cache. Therefore it is
possible that the literal may be present in both the data and instruction caches, resulting in waste of
space.
For maximum efficiency, the compiler should align all literal pools on cache boundaries and size
each pool to a multiple of 32 bytes (the size of a cache line). One additional optimization would be
group highly used literal pool references into the same cache line. The advantage is that once one
of the literals has been loaded, the other seven are available immediately from the data cache.