Intel Processor Computer Hardware User Manual


 
13-8 March, 2003 Developers Manual
Intel
®
80200 Processor based on Intel
®
XScale
Microarchitecture
Software Debug
13.5.2 Monitor Mode
In monitor mode, the processor handles debug exceptions like normal ARM exceptions. If debug
functionality is enabled (DCSR[31] = 1) and the processor is in Monitor mode, debug exceptions
cause either a data abort or a pre-fetch abort.
The following debug exceptions cause data aborts:
data breakpoint
external debug break
trace-buffer full break
The following debug exceptions cause pre-fetch aborts:
instruction breakpoint
BKPT instruction
The processor ignores vector traps during monitor mode.
When an exception occurs in monitor mode, the processor takes the following actions:
disables the trace buffer
sets DCSR.moe encoding
sets FSR[9]
R14_abt = PC of the next instruction to execute + 4 (for Data Aborts)
R14_abt = PC of the faulting instruction + 4 (for Prefetch Aborts)
SPSR_abt = CPSR
CPSR[4:0] = 0b10111 (ABORT mode)
CPSR[5] = 0
CPSR[6] = unchanged
CPSR[7] = 1
PC = 0xc (for Prefetch Aborts),
PC = 0x10 (for Data Aborts)
During abort mode, external debug breaks and trace buffer full breaks are internally pended. When
the processor exits abort mode, either through a CPSR restore or a write directly to the CPSR, the
pended debug breaks immediately generate a debug exception. Any pending debug breaks are
cleared out when any type of debug exception occurs.
When exiting, the debug handler should do a CPSR restore operation that branches to the next
instruction to be executed in the program under debug.