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Developer’s Manual March, 2003 7-15
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
7.2.11 Register 10: TLB Lock Down
Register 10 is used for locking down entries into the instruction TLB, and data TLB. (The protocol
for locking down entries can be found in Chapter 3, “Memory Management”.) Lock/unlock
operations on a TLB when the MMU is disabled have an undefined effect.
This register should be accessed as write-only. Reads from this register, as with an MRC, have an
undefined effect.
Table 7-16 shows the command for locking down entries in the instruction TLB, and data TLB.
The entry to lock is specified by the virtual address in Rd.
7.2.12 Register 11-12: Reserved
These registers are reserved. Reading and writing them yields unpredictable results.
Table 7-16. TLB Lockdown Functions
Function opcode_2 CRm Data Instruction
Translate and Lock I TLB entry 0b000 0b0100 MVA MCR p15, 0, Rd, c10, c4, 0
Translate and Lock D TLB entry 0b000 0b1000 MVA MCR p15, 0, Rd, c10, c8, 0
Unlock I TLB 0b001 0b0100 Ignored MCR p15, 0, Rd, c10, c4, 1
Unlock D TLB 0b001 0b1000 Ignored MCR p15, 0, Rd, c10, c8, 1