Filter
Top Products
Developer’s Manual March, 2003 11-1
Bus Controller
11
11.1 Introduction
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the
ARM* Architecture V5TE) Bus Controller Unit (BCU) is responsible for accessing off-chip
memory. It initiates bus cycles as documented in Chapter 10, “External Bus”.
The BCU is capable of queuing four outstanding transactions. This improves the performance of
the processor, because it does not need to wait for the result of a memory transaction before
initiating another.
If enabled by software, the BCU can protect data with an Error Correcting Code (ECC).
The BCU has software-accessible state in the form of coprocessor registers. All BCU registers
reside in Coprocessor 13 (CP13).
11.2 ECC
System software has the ability to request ECC checking on memory accesses. If the MMU
determines that a region of memory is protected by ECC, the BCU is responsible for checking and
generating ECC on accesses to that region. See Chapter 3, “Memory Management”, for a
description of the MMU.
The Intel
®
80200 processor data bus width is configured at reset-time to either 32 or 64 bits. Bus
configuration is detailed in Chapter 10, “External Bus”. The Intel
®
80200 processor only supports
ECC in the 64-bit mode.
When ECC is enabled for a memory region, the BCU never performs sub bus-width (64 bits)
writes to that region. If directed by the core to perform a sub bus-width write, the BCU performs a
bus-width read, merge in the appropriate bytes, and then perform a bus-width write with all
byte-enables asserted. This read-modify-write (RMW) is performed as an atomic transaction on the
external bus. This RMW behavior affects performance and can be avoided by specifying the region
as read/write-allocate and write-back cacheable in the MMU.
When writing to ECC-protected memory, the BCU always calculates the correct ECC bits and
writes them to memory at the same time as the data.
The ECC algorithm supported by the Intel
®
80200 processor uses eight bits to protect the data bus.
It can detect and correct any one-bit error, and it can detect any two-bit error.
Whenever the BCU checks ECC, it generates a syndrome -- a bitwise exclusive-OR of the expected
ECC versus the actual code received on the bus. Should an error be detected, this syndrome is
available to software to aid diagnosis.