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Developer’s Manual March, 2003 C-15
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Test Features
Figure C-5. Timing Diagram Illustrating the Loading of Data Register
TCK
TMS
Controller State
TDI
Data input to IR
IR shift-register
Parallel output of IR
Data input to TDR
TDR shift-register
Parallel output of TDR
Register Selected
TDO enable
TDO
Test-Logic-Reset
Exit1 - DR
Shift - DR
Capture - DR
Select - DR - Scan
Run - Test / Idle
Pause - DR
Exit2 - DR
Shift - DR
Exit1 - DR
Update - DR
Run - Rest / Idle
INACTIVEACTIVEINACTIVEINACTIVE
NEW DATA
INSTRUCTION
ID CODE
TEST DATA REGISTER
= Don't care or undefined
Select - DR - Scan
OLD DATA
ACT.
Select - IR - Scan