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Developer’s Manual March, 2003 xv
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
14-14 Semaphore Instruction Timings ....................................................................................................................9
14-15 CP15 Register Access Instruction Timings...................................................................................................9
14-16 CP14 Register Access Instruction Timings...................................................................................................9
14-17 SWI Instruction Timings...............................................................................................................................9
14-18 Count Leading Zeros Instruction Timings ....................................................................................................9
A-1 C and B encoding ..........................................................................................................................................3
B-1 Pipelines and Pipe stages...............................................................................................................................3
C-1 TAP Controller Pin Definitions.....................................................................................................................3
C-2 JTAG Instruction Set.....................................................................................................................................4
C-3 IEEE Instructions...........................................................................................................................................5
C-4 JTAG ID Register Value ...............................................................................................................................6