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Developer’s Manual March, 2003 1-1
Introduction
1
1.1 Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture High-Level Overview
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture, is the next generation in
the Intel
®
StrongARM* processor family (compliant with ARM* Architecture V5TE). It is
designed for high performance and low-power; leading the industry in mW/MIPs. The Intel
®
80200 processor integrates a bus controller and an interrupt controller around a core processor,
with intended embedded markets such as: handheld devices, networking, remote access servers,
etc. This technology is ideal for internet infrastructure products such as network and I/O
processors, where ultimate performance is critical for moving and processing large amounts of data
quickly.
The Intel
®
80200 processor incorporates an extensive list of architecture features that allows it to
achieve high performance. This rich feature set allows programmers to select the appropriate
features that obtains the best performance for their application. Many of the architectural features
added to Intel
®
80200 processor help hide memory latency which often is a serious impediment to
high performance processors. This includes:
• the ability to continue instruction execution even while the data cache is retrieving data from
external memory.
• a write buffer.
• write-back caching.
• various data cache allocation policies which can be configured different for each application.
• cache locking.
• and a pipelined external bus.
All these features improve the efficiency of the external bus.
The Intel
®
80200 processor has been equipped to efficiently handle audio processing through the
support of 16-bit data types and 16-bit operations. These audio coding enhancements center around
multiply and accumulate operations which accelerate many of the audio filter operations.
1.1.1 ARM* Architecture Compliance
ARM* Version 5 (V5) Architecture added floating point instructions to ARM* Version 4. The
Intel
®
80200 processor implements the integer instruction set architecture of ARM V5, but does
not provide hardware support of the floating point instructions.
The Intel
®
80200 processor provides the Thumb* instruction set (ARM* V5T) and the ARM* V5E
DSP extensions.
Backward compatibility with the first generation of Intel
®
StrongARM* products is maintained for
user-mode applications. Operating systems may require modifications to match the specific
hardware features of the Intel
®
80200 processor and to take advantage of the performance
enhancements added to the Intel
®
80200 processor.