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Developer’s Manual March, 2003 B-43
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Optimization Guide
B.5.6 Scheduling the MIA and MIAPH Instructions
The MIA instruction has an issue latency of 1 cycle. The result and resource latency can vary from
1 to 3 cycles depending on the values in the source register.
Consider the following code sample:
mia acc0, r2, r3
mia acc0, r4, r5
The second MIA instruction above can stall from 0 to 2 cycles depending on the values in the
registers r2 and r3 due to the 1 to 3 cycle resource latency.
Similarly, consider the following code sample:
mia acc0, r2, r3
mra r4, r5, acc0
The MRA instruction above can stall from 0 to 2 cycles depending on the values in the registers r2
and r3 due to the 1 to 3 cycle result latency.
The MIAPH instruction has an issue latency of 1 cycle, result latency of 2 cycles and a resource
latency of 2 cycles.
Consider the code sample shown below:
add r1, r2, r3
miaph acc0, r3, r4
miaph acc0, r5, r6
mra r6, r7, acc0
sub r8, r3, r4
The second MIAPH instruction would stall for 1-cycle due to a 2-cycle resource latency. The
MRA instruction would stall for 1-cycle due to a 2-cycle result latency. These stalls can be avoided
by rearranging the code as follows:
miaph acc0, r3, r4
add r1, r2, r3
miaph acc0, r5, r6
sub r8, r3, r4
mra r6, r7, acc0