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12-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Performance Monitoring
12.2 Clock Counter (CCNT; CP14 - Register 1)
The format of CCNT is shown in Table 12-1. The clock counter is reset to ‘0’ by Performance
Monitor Control Register (PMNC) or can be set to a predetermined value by directly writing to it.
It counts core clock cycles. When CCNT reaches its maximum value 0xFFFF,FFFF, the next clock
cycle causes it to roll over to zero and set the overflow flag (bit 6) in PMNC. An IRQ or FIQ is
reported if it is enabled via bit 6 in the PMNC register.
Table 12-1. Clock Count Register (CCNT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clock Counter
reset value: unpredictable
Bits Access Description
31:0 Read / Write
32-bit clock counter - Reset to ‘0’ by PMNC register.
When the clock counter reaches its maximum value
0xFFFF,FFFF, the next cycle causes it to roll over to zero
and generate an IRQ or FIQ if enabled.