Filter
Top Products
10-12 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.2.7 ECC
Software running on the Intel
®
80200 processor may configure pages in memory as being ECC
protected. For such pages, the Intel
®
80200 processor checks the ECC code associated with read
data, and generates an ECC code to associate with write data. The ECC code for a data element is
transported over the DCB bus. For 64-bit wide memories, an additional eight bits of width are
required to hold the ECC code. ECC is not supported in 32-bit memory systems.
If system software has indicated a memory region is ECC-protected, then the Intel
®
80200
processor will always process that memory at bus-width granularity (64-bits). Read data should
only be returned in multiples of 64-bits (8-, 16-, and 32-bit read requests should be answered with a
full 64 bits of data). Narrow writes to ECC-protected memory will be seen as read-modify-write
cycles of bus-width granularity, with Lock asserted during the transaction.
If the Intel
®
80200 processor is accessing a region of memory for which ECC is not enabled, it
drives zeroes on DCB during writes; receivers should ignore such values. On reads to such a
memory region, the Intel
®
80200 processor ignores the value on DCB, but this bus should be
driven to a valid level (all zeroes for example).
Note for 32-bit data bus systems: the system can satisfy this requirement on DCB by tieing its bits
low through pull-down resistors.
To ensure that a memory location has a valid ECC byte, software must write to an address before it
ever reads from it. This would not seem a problem, but the Intel
®
80200 processor aggressive
memory architecture can make it a challenge. When the data cache receives a write request, it may
respond by reading the associated line from memory, and then updating the specific address (data
cache operation is described in Chapter 6, “Data Cache”). This line-fill operation could be the first
access to that memory. So, a write to memory could trigger an ECC fault!
The solution is to write zeroes to memory before ECC is enabled. The Intel
®
80200 processor
writes zero into the DCB bus for this kind of transaction, and the ECC code for 64-bits of zero is
zero.
It is possible for the Intel
®
80200 processor to perform a write in which all byte-enables are not
asserted (i.e., BE#[7:0] = “11111111”). Systems that contains data memory for ECC should
interpret this to mean no data bytes or ECC bytes should be updated in response to the write.
Because the Intel
®
80200 processor only ever performs bus-width sized writes in ECC systems, a
simple solution to this requirement is to wire BE#[0] to the byte-enable of both the LSB and the
ECC byte.
To summarize the behavior of BE# on ECC-protected memory:
• Normal writes are 64-bits wide, so all BE# lines are asserted
• Reads do not activate the BE# lines, and should be answered with at least 64 bits of data
• If an ECC RMW operation detects an error on the read phase, it deasserts all BE# lines during
the write phase.