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10-20 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.3.6 Write Burst, Coalesced
Figure 10-10 shows a four word cache write caused by store requests coalesced in a write buffer.
The Len is 0x5 indicating four words. DValid is asserted for two consecutive cycles. The Intel
®
80200 processor drives the data as requested, but this time the byte enables are not all zeroes. The
byte enables here are asserted low only for those bytes that were stored by the instruction stream.
Any possible combination of byte enables can occur, with only the requirement that the first and
last data cycles have at least one byte enable asserted. (If the first or last data cycle had no bytes to
store, the transaction would have been issued as a shorter transaction).
Figure 10-10. Four Word Coalesced Write Burst
Wr Req
0x580
Wrd 0,1 Wrd 2,3
0xA5 0x30
ECC ECC
1
0
1
0x0
0ns 25ns 50ns 75ns
MCLK
ADS#/LEN[2]
Lock/LEN[1]
W/R#/LEN[0]
A
DValid
CWF
D
BE#
DCB
Abort