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13-44 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
The following steps describe the details for downloading code:
• Since the debug handler is responsible for synchronization during the code download, the
handler must be executing before the host can begin the download. The debug handler
execution starts when the application running on the Intel
®
80200 processor generates a debug
exception or when the host generates an external debug break.
• While the DBGTX JTAG instruction is in the JTAG IR (see Section 13.11.3, DBGTX JTAG
Command), the host polls DBG_SR[0], waiting for the debug handler to set it.
• When the debug handler gets to the point where it is OK to begin the code download, it writes
to TX, which automatically sets DBG_SR[0]. This signals the host it is OK to begin the
download. The debug handler then begins polling TXRXCTRL[31] waiting for the host to
clear it through the DBGRX JTAG register (to indicate the download is complete).
• The host writes LDIC to the JTAG IR, and downloads the code. For each line downloaded, the
host must invalidate the target line before downloading code to that line. Failure to invalidate a
line prior to writing it may cause unpredictable operation by the processor.
• When the host completes its download, the host must wait a minimum of 15 TCKs, then
switch the JTAG IR to DBGRX, and complete the handshaking (by scanning in a value that
sets DBG_SR[35]). This clears TXRXCTL[31] and allows the debug handler code to exit the
polling loop. The data scanned into DBG_SR[34:3] is implementation specific.
• After the handler exits the polling loop, it branches to the downloaded code.
Note that this debug handler stub must reside in the instruction cache and execute out of the cache
while doing the synchronization. The processor should not be doing any code fetches to external
memory while code is being downloaded.