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Developer’s Manual March, 2003 13-37
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
All packets are 33 bits in length. Bits [2:0] of the first packet specify the function to execute. For
functions that require an address, bits[32:6] of the first packet specify an 8-word aligned address
(Packet1[32:6] = VA[31:5]). For Load Main IC and Load Mini IC, 8 additional data packets are
used to specify 8 ARM instructions to be loaded into the target instruction cache. Bits[31:0] of the
data packets contain the data to download. Bit[32] of each data packet is the value of the parity for
the data in that packet.
As shown in Figure 13-11, the first bit shifted in TDI is bit 0 of the first packet. After each 33-bit
packet, the host must take the JTAG state machine into the Update_DR state. After the host does an
Update_DR and returns the JTAG state machine back to the Shift_DR state, the host can
immediately begin shifting in the next 33-bit packet.
Figure 13-11. Format of LDIC Cache Functions
25
00
31
Invalidate IC Line
x0xx
. . .
Invalidate Mini IC
VA[31:5]
Load Main IC
VA[31:5]
.
.
.
Data Word 0
Data Word 7
Load Mini IC
and
(CMD = 0b010)
(CMD = 0b011)
- indicates first
- indicates last
bit shifted in
bit shifted in
0 00
000 0
0
0
0 0
CMD
32
0
1
2531 032
2531 032
P
P