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Developer’s Manual March, 2003 9-1
Interrupts
9
9.1 Introduction
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the
ARM* Architecture V5TE) supports a variety of external and internal interrupt sources. The
Interrupt Control Unit (ICU) controls how the Intel
®
80200 processor reacts to these interrupts.
Ultimately, all interrupt sources are combined into one of two internal interrupts: IRQ and FIQ.
These interrupts correspond to the IRQ and FIQ described in the ARM Architecture Reference
Manual.
The two interrupt signals that enter the chip are FIQ# (fast interrupt) and IRQ# (normal interrupt).
These signals must be asserted and held low to interrupt the processor.
The internal interrupt sources originate in the Bus Controller Unit (see Chapter 11, “Bus
Controller”) and the Performance Monitoring Unit (see Chapter 12, “Performance Monitoring”).
To allow flexible system design, these interrupts may be steered under software control to act
equivalently to either FIQ or IRQ.
All interrupts are level sensitive: interrupt sources must keep asserting the interrupt signal until
software causes the source to deassert it.
All interrupt sources are individually maskable with the ICUs Interrupt Control register (INTCTL).
Additionally, all interrupts may be quickly disabled by altering the F and I bits in the CPSR as
specified in the ARM Architecture Reference Manual.
When software running on the Intel
®
80200 processor is vectored to an Interrupt Service Routine
(ISR), it may query the ICUs Interrupt Source register (INTSRC) to quickly determine the source
of the interrupt.
9.2 External Interrupts
The two external interrupts, FIQ# and IRQ#, go through synchronization logic before being
sampled by the ICU.
External interrupts must be held asserted until cleared at the interrupting source by software. The
Intel
®
80200 processor does not latch the external interrupt signals. Enabled interrupts that are
deasserted before software enters the interrupt service routine causes UNPREDICTABLE behavior.