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7-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
5:3 Read / Write Ignored Instruction cache associativity = 0b101 = 32 kB
2 Read-as-Zero / Write Ignored Reserved
1:0 Read / Write Ignored Instruction cache line length = 0b10 = 8 words/line
Table 7-5. Cache Type Register (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00001011000110101010000110101010
reset value: As Shown
Bits Access Description