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Developer’s Manual March, 2003 7-19
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
Table 7-20. Coprocessor Access Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
C
P
1
3
C
P
1
2
C
P
1
1
C
P
1
0
C
P
9
C
P
8
C
P
7
C
P
6
C
P
5
C
P
4
C
P
3
C
P
2
C
P
1
C
P
0
reset value: 0x0000,0000
Bits Access Description
31:16 Read-unpredictable / Write-as-Zero Reserved - Program to zero for future compatibility
15:14 Read-as-Zero/Write-as-Zero Reserved - Program to zero for future compatibility
13:0 Read / Write
Coprocessor Access Rights-
Each bit in this field corresponds to the access rights for
each coprocessor.
For each bit:
0 = Access denied. Attempts to access corresponding
coprocessor generates an undefined exception.
1 = Access allowed. Includes read and write accesses.
Setting any of bits 12:1 has an undefined effect.