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Developer’s Manual March, 2003 10-19
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.3.5.1 Write Burst
Figure 10-9 shows a four word write caused by the eviction of a half cache line. In this case, the
Len is 0x5 indicating four words. DValid is asserted for two consecutive cycles here, but the two
cycles could be spread out. In this case the Intel
®
80200 processor drives the data as requested,
along with BE# of 0x00 each cycle, indicating that all the bytes are being written.
Figure 10-9. Four Word Eviction Write
Wr Req
0x240
W 0,1 W 2,3
0x00 0x00
1
0
1
0x0
0ns 25ns 50ns 75ns
MCLK
ADS#/LEN[2]
Lock/LEN[1]
W/R#/LEN[0]
A
DValid
CWF
D
BE#
DCB
Abort