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14-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Performance Considerations
14.4.4 Multiply Instruction Timings
Table 14-7. Multiply Instruction Timings (Sheet 1 of 2)
Mnemonic
Rs Value
(Early Termination)
S-Bit
Value
Minimum
Issue Latency
Minimum Result
Latency
1
Minimum Resource
Latency (Throughput)
MLA
Rs[31:15] = 0x00000
or
Rs[31:15] = 0x1FFFF
01 2 1
12 2 2
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
01 3 2
13 3 3
all others
01 4 3
14 4 4
MUL
Rs[31:15] = 0x00000
or
Rs[31:15] = 0x1FFFF
01 2 1
12 2 2
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
01 3 2
13 3 3
all others
01 4 3
14 4 4
SMLAL
Rs[31:15] = 0x00000
or
Rs[31:15] = 0x1FFFF
0 2 RdLo = 2; RdHi = 3 2
13 3 3
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
0 2 RdLo = 3; RdHi = 4 3
14 4 4
all others
0 2 RdLo = 4; RdHi = 5 4
15 5 5
SMLALxy N/A N/A 2 RdLo = 2; RdHi = 3 2
SMLAWy N/A N/A 1 3 2
SMLAxy N/A N/A 1 2 1
SMULL
Rs[31:15] = 0x00000
or
Rs[31:15] = 0x1FFFF
0 1 RdLo = 2; RdHi = 3 2
13 3 3
Rs[31:27] = 0x00
or
Rs[31:27] = 0x1F
0 1 RdLo = 3; RdHi = 4 3
14 4 4
all others
0 1 RdLo = 4; RdHi = 5 4
15 5 5
SMULWy N/A N/A 1 3 2
SMULxy N/A N/A 1 2 1
UMLAL
Rs[31:15] = 0x00000
0 2 RdLo = 2; RdHi = 3 2
13 3 3
Rs[31:27] = 0x00
0 2 RdLo = 3; RdHi = 4 3
14 4 4
all others
0 2 RdLo = 4; RdHi = 5 4
15 5 5