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Developer’s Manual March, 2003 1-3
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Introduction
1.1.2.2 Memory Management
The Intel
®
80200 processor implements the Memory Management Unit (MMU) Architecture
specified in the ARM Architecture Reference Manual. The MMU provides access protection and
virtual to physical address translation.
The MMU Architecture also specifies the caching policies for the instruction cache and data
memory. These policies are specified as page attributes and include:
• identifying code as cacheable or non-cacheable
• selecting between the mini-data cache or data cache
• write-back or write-through data caching
• enabling data write allocation policy
• and enabling the write buffer to coalesce stores to external memory
Chapter 3, “Memory Management”discusses this in more detail.
1.1.2.3 Instruction Cache
The Intel
®
80200 processor implements a 32-Kbyte, 32-way set associative instruction cache with
a line size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte read
request to external memory. A mechanism to lock critical code within the cache is also provided.
Chapter 4, “Instruction Cache”discusses this in more detail.
1.1.2.4 Branch Target Buffer
The Intel
®
80200 processor provides a Branch Target Buffer (BTB) to predict the outcome of
branch type instructions. It provides storage for the target address of branch type instructions and
predicts the next address to present to the instruction cache when the current instruction address is
that of a branch.
The BTB holds 128 entries. See Chapter 5, “Branch Target Buffer”for more details.
1.1.2.5 Data Cache
The Intel
®
80200 processor implements a 32-Kbyte, a 32-way set associative data cache and a
2-Kbyte, 2-way set associative mini-data cache. Each cache has a line size of 32 bytes, supports
write-through or write-back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by
coprocessor 15.
Chapter 6, “Data Cache”discusses all this in more detail.
The Intel
®
80200 processor allows applications to re-configure a portion of the data cache as data
RAM. Software may place special tables or frequently used variables in this RAM. See
Section 6.4, “Re-configuring the Data Cache as Data RAM” on page 6-12 for more information on
this.