Filter
Top Products
4-6 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Instruction Cache
4.3 Instruction Cache Control
4.3.1 Instruction Cache State at RESET
After reset, the instruction cache is always disabled, unlocked, and invalidated (flushed).
4.3.2 Enabling/Disabling
The instruction cache is enabled by setting bit 12 in coprocessor 15, register 1 (Control Register).
This process is illustrated in Example 4-2, Enabling the Instruction Cache.
Example 4-2. Enabling the Instruction Cache
; Enable the ICache
MRC P15, 0, R0, C1, C0, 0 ; Get the control register
ORR R0, R0, #0x1000 ; set bit 12 -- the I bit
MCR P15, 0, R0, C1, C0, 0 ; Set the control register
CPWAIT