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Developer’s Manual March, 2003 13-25
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.11.6.4 DBG.V
The debugger sets this bit to indicate the data scanned into DBG_SR[34:3] is valid data to write to
RX. DBG.V is an input to the RX Write Logic and is also cleared by the RX Write Logic.
When this bit is set, the data scanned into the DBG_SR is written to RX following an Update_DR.
If DBG.V is not set and the debugger does an Update_DR, RX is unchanged.
This bit does not affect the actions of DBG.FLUSH or DBG.D.
13.11.6.5 DBG.RX
DBG.RX is written into the RX register based on the output of the RX Write Logic. Any data that
needs to be sent from the debugger to the processor must be loaded into DBG.RX with DBG.V set
to 1. DBG.RX is loaded from DBG_SR[34:3] when the JTAG enters the Update_DR state.
DBG.RX is written to RX following an Update_DR when the RX Write Logic enables the RX
register.
13.11.6.6 DBG.D
DBG.D is provided for use during high speed download. This bit is written directly to
TXRXCTRL[29]. The debugger sets DBG.D when downloading a block of code or data to the
Intel
®
80200 processor system memory. The debug handler then uses TXRXCTRL[29] as a branch
flag to determine the end of the loop.
Using DBG.D as a branch flags eliminates the need for a loop counter in the debug handler code.
This avoids the problem were the debugger’s loop counter is out of synchronization with the debug
handler’s counter because of overflow conditions that may have occurred.
13.11.6.7 DBG.FLUSH
DBG.FLUSH allows the debugger to flush any previous data written to RX. Setting DBG.FLUSH
clears TXRXCTRL[31].
13.11.7 Debug JTAG Data Register Reset Values
Upon asserting TRST, the DEBUG data register is reset. Assertion of the reset pin does not affect
the DEBUG data register. Table 13-13 shows the reset and TRST values for the data register. Note:
these values apply for DBG_REG for SELDCSR, DBGTX and DBGRX.
Table 13-13. DEBUG Data Register Reset Values
Bit TRST RESET
DBG_REG[0] 0 unchanged
DBG_REG[1] 0 unchanged
DBG_REG[33:2] unpredictable unpredictable
DBG_REG[34] 0 unchanged