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A-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Compatibility: Intel
®
80200 Processor vs. SA-110
A.3.4 Write Buffer Behavior
Definition of Coalescing: Coalescing means bringing together a new store operation with an
existing store operation already resident in the write buffer. The new
store is placed in the same write buffer entry as an existing store when
the address of the new store falls in the 4-word aligned address of the
existing entry. This includes, in PCI terminology, write merging, write
collapsing, and write combining.
There is a difference in how stores are coalesced to existing entries in the write buffer. When
coalescing is enabled, SA-110 only coalesces to the last entry placed in the write buffer. The Intel
®
80200 processor can coalesce to any entry in the write buffer. The Intel
®
80200 processor also
added a global coalesce disable bit located in the Control Register (CP15, register 1, opcode_2=1).
Another difference between SA-110 and the Intel
®
80200 processor is that the write buffer is
always enabled on the Intel
®
80200 processor. Bit 3 of the Control Register (CP15, register 1,
opcode_2=0) was used in SA-110 to enable/disable the write buffer. For the Intel
®
80200
processor, this bit is always set to 1.
Memory references are rearranged if that would cause incorrect program behavior (see Section 6.5,
“Write Buffer/Fill Buffer Operation and Control” on page 6-16).
A.3.5 External Aborts
External aborts are imprecise exceptions on the Intel
®
80200 processor. External aborts may be
generated by external memory when, for example, there is a parity error detected during a memory
access. Since the Intel
®
80200 processor continues instruction execution during external memory
requests, the PC that is saved in R14 when the exception is reported may not be the PC of the
offending instruction. Many instructions may have executed after the offending instruction.
SA-110 always stalls the processor when there was an external load request or when an external
write request occurs with C=0 and B=0. External aborts detected on these requests would be
precise, meaning the PC that is saved in R14_ABORT when the exception is reported is the address
of the offending instruction. The Intel
®
80200 processor also stalls the processor for these requests
but an external abort on these requests would not be precise. The value in R14_ABORT when the
exception is reported would not be that of the offending instruction.
Software relying on this feature of SA-110 may not be compatible with the Intel
®
80200 processor.