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Developer’s Manual March, 2003 9-3
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Interrupts
9.3.1 INTCTL
INTCTL is used to specify what interrupts are disabled (masked).
Table 9-1. Interrupt Control Register (CP13 register 0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B
M
P
M
I
M
F
M
reset value: writeable bits set to 0
Bits Access Description
31:4
Read-unpredictable /
Write-as-Zero
Reserved
3 Read / Write
BM -BCU Mask
Controls whether BCU interrupts are enabled
0 = disable interrupt
1 = enable interrupt
2 Read / Write
PM -PMU Mask
Controls whether PMU interrupts are enabled
0 = disable interrupt
1 = enable interrupt
1 Read / Write
IM - IRQ# mask
Enables external interrupts from the IRQ# pin
0 = disable interrupt
1 = enable interrupt
0 Read / Write
FM -FIQ# mask
Enables external interrupts from the FIQ# pin
0 = disable interrupt
1 = enable interrupt