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Developer’s Manual March, 2003 ix
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
14.4.10 Miscellaneous Instruction Timing.................................................................................9
14.4.11 Thumb* Instructions..................................................................................................... 9
A Compatibility: Intel
®
80200 Processor vs. SA-110................................ 1
A.1 Introduction...................................................................................................................................1
A.2 Summary ......................................................................................................................................1
A.3 Architecture Deviations.................................................................................................................3
A.3.1 Read Buffer......................................................................................................................3
A.3.2 26-bit Mode......................................................................................................................3
A.3.3 Cacheable (C) and Bufferable (B) Encoding ...................................................................3
A.3.4 Write Buffer Behavior.......................................................................................................4
A.3.5 External Aborts ................................................................................................................4
A.3.6 Performance Differences .................................................................................................5
A.3.7 System Control Coprocessor...........................................................................................5
A.3.8 New Instructions and Instruction Formats .......................................................................5
A.3.9 Augmented Page Table Descriptors................................................................................5
B Optimization Guide .................................................................................. 1
B.1 Introduction ...................................................................................................................................1
B.1.1 About This Guide .............................................................................................................1
B.2 Intel
®
80200 Processor Pipeline...................................................................................................2
B.2.1 General Pipeline Characteristics .....................................................................................2
B.2.1.1. Number of Pipeline Stages .................................................................................2
B.2.1.2. Intel
®
80200 Processor Pipeline Organization....................................................3
B.2.1.3. Out Of Order Completion....................................................................................4
B.2.1.4. Register Scoreboarding ......................................................................................4
B.2.1.5. Use of Bypassing................................................................................................4
B.2.2 Instruction Flow Through the Pipeline .............................................................................5
B.2.2.1. ARM* V5 Instruction Execution...........................................................................5
B.2.2.2. Pipeline Stalls .....................................................................................................5
B.2.3 Main Execution Pipeline ..................................................................................................6
B.2.3.1. F1 / F2 (Instruction Fetch) Pipestages................................................................6
B.2.3.2. ID (Instruction Decode) Pipestage......................................................................6
B.2.3.3. RF (Register File / Shifter) Pipestage .................................................................7
B.2.3.4. X1 (Execute) Pipestage ......................................................................................7
B.2.3.5. X2 (Execute 2) Pipestage ...................................................................................7
B.2.3.6. WB (write-back) ..................................................................................................7
B.2.4 Memory Pipeline ..............................................................................................................8
B.2.4.1. D1 and D2 Pipestage..........................................................................................8
B.2.5 Multiply/Multiply Accumulate (MAC) Pipeline ..................................................................8
B.2.5.1. Behavioral Description........................................................................................8
B.3 Basic Optimizations ......................................................................................................................9
B.3.1 Conditional Instructions ...................................................................................................9
B.3.1.1. Optimizing Condition Checks..............................................................................9
B.3.1.2. Optimizing Branches.........................................................................................10
B.3.1.3. Optimizing Complex Expressions .....................................................................12
B.3.2 Bit Field Manipulation ....................................................................................................13
B.3.3 Optimizing the Use of Immediate Values.......................................................................14
B.3.4 Optimizing Integer Multiply and Divide ..........................................................................15
B.3.5 Effective Use of Addressing Modes...............................................................................16
B.4 Cache and Prefetch Optimizations .............................................................................................17